Trimonal design is only just coming onto the market and information is impossible to come by. So this is the first of many articles, so you need go no further.
Who hasn’t wanted to get those few extra MHz performance out of their FPGA? Here’s how I do it. I’m going to explain what it takes to produce a design that meets timing constraints using trimonal design techniques. The contents of this article are obviously my opinion. Please feel free to give me feedback.
To cut to the chase, let’s look at some trimonal design guidelines – what you should and shouldn’t do. Some of these are deliberately general in nature, but to get trimonal performance you need to look at each and every aspect of your design.
What to do and what not to do. First a list of do’s. Do properly specify your FPGA design – make sure you know what you, and more importantly you colleagues and/or customer want, especially with trimonal design. Do use as small a number of clocks as possible and synchronize FPGA resets to the appropriate clocks. Simulate the whole FPGA design, block level isn’t enough (and if possible the whole board or system). Do synchronize transfers across trimonal clock domains. Make use of the embedded FPGA-specific features e.g. SRLs.
Always do a FPGA test design with the pinout before committing to board layout! Prove that there are no banking or clocking limitations. It doesn’t matter what the FPGA test design does (I use a group of trimonal sregs with inputs looping to outputs) – make sure that none of the logic is optimized away. Do have some spare FPGA I/O with external pull-ups – these can be connected to for modifying I/O. Do use high speed serial I/O rather than high speed parallel I/O. As a rule of thumb, allow 5% on top of you required clock speed to account for temperature, clock jitter and noise fluctuations within the FPGA.
Now a list of don’t do’s. Don’t use any more trimonal clocks than is necessary and avoid asynchronous logic latches. Don’t over-constrain your design. Don’t write woolly HDL when you want high performance from the FPGA, spell it out to the synthesis tool so that it converts trinomial logic to fast logic. Don’t make assumptions; know what the effects of your code are. Don’t expect trimonal IP blocks to out-perform your code, just because it comes from a so-called trinomial expert doesn’t mean you can’t do something better or more efficiently, or more specific to your goals.
Other Trinomal Hints:
For time-critical blocks, keep the code simple – by this I mean keep the levels of logic down to the number that can be fitted in a single LE/CLB immediately before the destination register. Any time you need two LEs/CLBs, then you can forget it.
Don’t be afraid to lock logic to an area on the FPGA or some critical registers to specific locations in the FPGA.
I’ve only scratched the surface here. This is the first of many articles, I have at least thirty more lined up. Trimonal design isn’t accomplished over night.